FIG. 1 (Prior Art) is a simplified diagram of a TCP packet. FIG. 2 is a simplified diagram of a network interface card (NIC) 100 card called an intelligent network interface card (INIC). One of the operations the INIC performs is to read data for a TCP packet out of host memory 101 on a host computer 102 and to transmit that data as the data payload of a TCP message onto a network 107.
A difficulty associated with performing this operation quickly is that the checksum of the TCP packet is located near the front of the packet before the data payload. The checksum is a function of all the data of the data payload. Consequently all the data of the payload must generally be transferred to the INIC 100 before the checksum can be generated. Consequently, in general, all the data of the payload is received onto the INIC card, the checksum 104 is generated, the checksum 104 is then combined with the data payload in DRAM 105 to form the complete TCP packet 106, and the complete TCP packet 106 is then transferred from DRAM 105 to the network 107.
FIG. 2 illustrates this flow of information. Arrow 108 illustrates the flow of data from host memory 101 and across PCI bus 103 to DRAM 105 located on INIC card 100. While the data is being transferred, processor 109 on INIC card 100 builds the TCP header 110 in faster SRAM 111. The TCP header is formed in SRAM 111 rather than DRAM 105 because processor 109 needs to perform multiple operations on the header 110 as it is assembled and doing such multiple operations from relatively slow DRAM would unduly slow down processor 109. When all the data has been received onto the INIC 100, processor 109 is able to determine the checksum 104. The complete TCP header 110 including the correct checksum 104 is at that point residing in SRAM 111. Arrow 112 represents the assembly and writing of the complete header 110 from processor 109 to SRAM 111.
Once the complete header 110 is assembled, it is transferred from SRAM 111 to DRAM 105 in a relatively slow write to DRAM 105. Arrow 113 illustrates this transfer. Once the complete TCP packet 106 is assembled in DRAM 105, the complete packet 106 is output from DRAM 105 to the network 107. In the example of FIG. 2, this transfer is represented by arrow 114.
Unfortunately, the writing to DRAM 105 is often a relatively slow process and this writing can only begin once all the data has been received onto the INIC card. The result is an undesirable latency in the outputting of the TCP packet onto the network. A solution is desired.